Comp Arch - Lecture 6

Energy efficiency, thermal management, and reliability.

Buffer overflows, Spectre, and Meltdown.

Executing multiple instructions from a single thread simultaneously.

If a piece of data is accessed, data nearby in memory is likely to be accessed soon.

Small, fast storage locations in the CPU used to hold data and instructions being actively used.

Using cache memory to reduce the average access time to memory.

Data is written to both the cache and main memory simultaneously.

The implementation of the ISA, including the organization of the CPU, cache, and memory system.

Minimizing power consumption to reduce heat and extend battery life.

Occur when a program writes data beyond the allocated buffer.

Executing multiple threads simultaneously on different cores or processors.

Small, fast memory used to store frequently accessed data.

Instruction-level parallelism (ILP) and thread-level parallelism (TLP).

Data is written only to the cache, and main memory is updated later.

The interface between hardware and software, defining instructions, data types, addressing modes, etc.

Includes all other hardware components in a computing system, such as memory controllers, I/O devices, etc.

Vulnerabilities that allow attackers to access sensitive data by exploiting speculative execution.

Direct-mapped, fully associative, and set-associative.

Field-Programmable Gate Arrays.

Fetching, decoding, executing, and storing.

Executing multiple instructions from a single thread simultaneously.

Adding extra components or data to detect and correct errors.

Managing and dissipating heat generated by the processor and other components.

Complex Instruction Set Computing.

Each memory location maps to a specific location in the cache.

Executing multiple threads simultaneously on different cores or processors.

Codes used to detect and correct errors in memory and storage systems.

Reduced Instruction Set Computing.

Ensuring that the system operates correctly and reliably over its intended lifespan.

Accelerators, FPGAs, and ASICs.

Any memory location can be stored in any location in the cache.

Retrieving the instruction from memory.

Techniques used to improve the performance of a computer system.

Designing systems that can continue to operate correctly even in the presence of faults.

The overlapping of the execution of multiple instructions to improve throughput.

Specialized hardware units designed to accelerate specific tasks.

A processor with multiple cores on a single chip, allowing multiple threads to execute simultaneously.

The primary memory used to store programs and data that are currently being used by the CPU.

Determining what operation needs to be performed.

Defines what operations the CPU can perform.

Designing processors to perform well on specific types of workloads.

Specialized processors designed for parallel processing, particularly for graphics and compute-intensive tasks.

Using architectural features to enhance security.

Field-Programmable Gate Arrays; integrated circuits that can be configured after manufacturing.

Application-Specific Integrated Circuits.

Computer architecture deals with the engineering considerations involved in designing a computer.

Long-term storage for data and programs (e.g., hard drives, SSDs).

Performing the operation.

Pipelining, parallelism, and caching.

MIPS, ARM, x86

Address space layout randomization (ASLR) and hardware-based security features.

Amdahl's Law

Application-Specific Integrated Circuits; integrated circuits designed for a specific application.

Dynamic Voltage and Frequency Scaling.

Temporal Locality and Spatial Locality

Superscalar execution and out-of-order execution.

Overlapping the execution of multiple instructions to improve throughput.

Dynamic Voltage and Frequency Scaling (DVFS).

Complex Instruction Set Computing; has a large set of complex instructions.

It states that the speedup of a program using multiple processors is limited by the fraction of the program that can be parallelized.

Address Space Layout Randomization.

Executing multiple instructions in the same clock cycle.

Performing multiple operations simultaneously using multiple execution units or cores.

Adjusting the voltage and frequency of the processor based on workload to reduce power consumption.

Randomizing the memory locations of key data areas to make it harder for attackers to exploit vulnerabilities.

Reduced Instruction Set Computing; has a smaller set of simpler instructions.

If a piece of data is accessed, it is likely to be accessed again in the near future.

Executing instructions in a different order than they appear in the program to avoid stalls.

A compromise between direct-mapped and fully associative, where the cache is divided into sets, and each memory location maps to a specific set.

Heat sinks, fans, and liquid cooling.

Features built into the hardware to protect against certain types of attacks.

Instruction Set Architecture (ISA), Microarchitecture, and System Design.

Storing the result of the operation.

The ability to perform multiple operations simultaneously using multiple execution units or cores.

Write-through and write-back.

Redundancy, error correction codes, and fault tolerance.

Design choices that impact a system's security.

The interface between hardware and software, defining instructions, data types, addressing modes, etc.

Registers, cache, main memory, and secondary storage.

Multicore processors and GPUs.

LIFO (Last In, First Out)

Interrupt Enable Flag

SHL (Shift Logical Left), SHR (Shift Logical Right)

Pop return address from stack and Jump to that address

Carry Flag

Performs a bitwise AND operation like the AND instruction, but does not modify the source and destination.

Direction Flag

The return address (IP) is pushed to the stack.

Parity Flag

Segment addresses are shifted 4 bits to the left before adding the offset.

AND, OR, XOR, NOT

Auxiliary Carry Flag

Get all general-purpose registers from the stack.

Makes the program execution jump to a specific label or address unconditionally.

Sign Flag

Stack grows towards smaller addresses; stack size is static and predetermined.

PUSH all general-purpose registers onto the stack.

Trace (Trap) Flag

SAL (Shift Arithmetic Left), SAR (Shift Arithmetic Right)

Get the flags register from the stack.

RCL (Rotate Left Through Carry), RCR (Rotate Right Through Carry)

Full 3 hours, in person, written by hand without outside notes, worth 24% of final grade, covers lectures 1-5.

Uses the CX register as a loop counter and decrements it, looping if CX ≠ 0.

Defined after they are called, before end of code segment

ROL (Rotate Left), ROR (Rotate Right)

je (jump if equal), jg (jump if greater), jl (jump if less), etc.

Callee-saved: procedure clears out some registers for its own use. Caller-saved: calling program saves the registers that it does not want the procedure to overwrite.

Procedures should not push to stack without popping

Jump to effective address given by operand

Store the flags register in the stack.

Makes the program execution jump to a specific label or address if the condition is true.

The OS steps in and kills program.

Use registers, or pass parameters on the stack.

push ax; push dx; call myproc; ...

Flags are set according to the result of the subtraction operation.

PUSH (push operand onto stack), POP (pop operand from stack)

SP holds an effective address, while SS holds a physical address.

Zero Flag

Used to compare two 8, 16, or 32-bit numbers by performing subtraction without saving the result.

CLC (Clear Carry Flag), STC (Set Carry Flag), CLD (Clear Direction Flag), STD (Set Direction Flag), CLI (Clear Interrupt Flag), STI (Set Interrupt Flag), CMC (Complement Carry Flag), LAHF (Load AH from flags)

Overflow Flag

MASM generates code for 8086 by default. use .186, .286, .386 directive in the first line of your code to solve.